This invention relates to a semiconductor memory, and more particularly to a differential read-clock generator within a memory chip.
Semiconductor memories are commercially available in a wide range of storage capacity and operating speeds. Typically, the storage capacity of semiconductor memory chips is standardized at 16 bits, 256 bits, 512 bits, 1024 bits, 2048 bits, 4096 bits, 8192 bits, or 16,284 bits. But these chips are combined in a countless variety of ways to form many different sized memories.
The operating speed of a memory generally refers to the memory's read time, and write time. Read time refers to the time interval required to access data from the memory, and write time refers to the time interval required to write data into the memory. The speed at which these operations can be performed is critical because the trend over the last 10 years of the digital equipment which uses these memories, has been to continually require higher operating speeds. Therefore, much effort has been spent in the semiconductor industry to develop higher speed memories.
Several factors influence the read time of a semiconductor chip. In the past, one factor was a time delay that occurred between the stabilization of the sense amplifiers within the memory chip, and the gating of the sense amplifier's output to the data output lead on the chip. This time delay was purposely inserted to ensure that the sense amplifiers had stabilized before their output was gated. The capacitive loading on the sense amplifiers is delicately balanced during a read operation, and this balance would be upset and result in read errors if the sense amplifiers were gated before they stabilized.
This time delay typically was implemented by an R-C read-clock generator, which utilized two transistors, A and B, and a capacitor to act as an R-C timing network. Transistor A had a source coupled to a voltage source V.sub.dd, and had a drain coupled to a node N. Transistor B had a source coupled to node N and had a drain coupled to ground. The capacitor also coupled between node N and ground.
Prior to a read operation, transistor A was turned on and the capacitor was thus charged. During a read operation, transistor B was turned on and the capacitor was thus discharged. The discharge time was designed to be longer than the time it took the sense amplifiers to stabilize; and the sense amplifiers were gated when the discharge completed.
One problem with this R-C read-clock generator was that the R-C time constant always had to be made significantly larger, rather than equal to, the stabilization time of the sense amplifiers. This was because the timing parameters of the R-C network and the sense amplifiers were impossible to match exactly due to the different architecture of the two circuits. Sense amplifiers are basically a differential voltage sensory device, rather than a simple R-C discharge network. This difference in architecture also caused the timing parameters of two circuits to behave differently with respect to temperature changes. The result was that the read time of the memory chip was undesirably long.
It is, therefore, one object of the invention to provide a memory with an improved read time.
Another object of the invention is to provide an improved memory read-clock generator.
Another object of the invention is to provide a read clock generator with a differential voltage sensing architecture.
A further object of the invention is to provide a read clock generator which produces an output signal within a few nano-seconds of the time when the sense amplifiers have stabilized.
Still another object of the invention is to provide a read clock generator with timing parameters that vary with temperatures similar to the timing parameters of the sense amplifiers.